There has been a lot of interest in low-density parity check block codes (LDPC-BCs) in recent years, primarily due to the efficiency of the codes and the ability to decode them with relatively simple circuits. Larger and faster LDPC-BC encoder and decoder implementations can be devised to meet the ever-increasing demands of modern telecommunication systems. However, many of today's wireline and wireless communication systems are packet or frame based, such as those based on Ethernet communication protocols. Applying LDPC-BCs to such systems presents several challenges. For example, how does one accommodate the random Ethernet frame size within a fixed LDPC-BC block size? What happens if an Ethernet frame to be transmitted is just slightly larger than an integer multiple of the block size? How are the LDPC-BC blocks to be delimited at the decoder so that it can synchronize with the encoder?
Low-density parity-check convolutional codes (LDPC-CCs) address some of these challenges by combining the advantages of LDPC-BCs with the ability to encode and decode arbitrary lengths of data. Another advantage of LDPC-CCs is that encoding and decoding can be done from a known state. This capability can greatly reduce the probability of an error over the first bytes of a frame, which is where important information is located with some protocols. However, at least some current architectures for LDPC-CC decoders tend to be register-intensive and as such are not optimal for FPGA and similar semiconductor implementations.